#name: s390x base/index register 0
#objdump: -dr

.*: +file format .*

Disassembly of section .text:

.* <foo>:
.*:	92 20 10 10 [	 ]*mvi	16\(%r1\),32
.*:	92 20 00 10 [	 ]*mvi	16,32
.*:	92 20 00 10 [	 ]*mvi	16,32
.*:	92 20 00 10 [	 ]*mvi	16,32
.*:	92 20 00 00 [	 ]*mvi	0,32
.*:	92 00 00 00 [	 ]*mvi	0,0
.*:	5a 12 30 10 [	 ]*a	%r1,16\(%r2,%r3\)
.*:	5a 10 30 10 [	 ]*a	%r1,16\(%r3\)
.*:	5a 10 30 10 [	 ]*a	%r1,16\(%r3\)
.*:	5a 10 30 10 [	 ]*a	%r1,16\(%r3\)
.*:	5a 10 30 10 [	 ]*a	%r1,16\(%r3\)
.*:	5a 12 00 10 [	 ]*a	%r1,16\(%r2,0\)
.*:	5a 12 00 10 [	 ]*a	%r1,16\(%r2,0\)
.*:	5a 12 00 10 [	 ]*a	%r1,16\(%r2,0\)
.*:	5a 10 00 10 [	 ]*a	%r1,16
.*:	5a 10 00 10 [	 ]*a	%r1,16
.*:	5a 10 00 10 [	 ]*a	%r1,16
.*:	5a 10 00 10 [	 ]*a	%r1,16
.*:	5a 10 00 10 [	 ]*a	%r1,16
.*:	5a 10 00 10 [	 ]*a	%r1,16
.*:	5a 10 00 10 [	 ]*a	%r1,16
.*:	5a 10 00 10 [	 ]*a	%r1,16
.*:	5a 10 00 10 [	 ]*a	%r1,16
.*:	5a 10 00 10 [	 ]*a	%r1,16
.*:	5a 10 00 00 [	 ]*a	%r1,0
.*:	5a 00 00 00 [	 ]*a	%r0,0
.*:	5a 00 00 00 [	 ]*a	%r0,0
.*:	d2 00 10 10 20 20 [	 ]*mvc	16\(1,%r1\),32\(%r2\)
.*:	d2 00 00 10 20 20 [	 ]*mvc	16\(1,0\),32\(%r2\)
.*:	d2 00 00 10 20 20 [	 ]*mvc	16\(1,0\),32\(%r2\)
.*:	d2 00 00 10 20 20 [	 ]*mvc	16\(1,0\),32\(%r2\)
.*:	d2 00 00 10 20 20 [	 ]*mvc	16\(1,0\),32\(%r2\)
.*:	d2 00 10 10 00 20 [	 ]*mvc	16\(1,%r1\),32
.*:	d2 00 10 10 00 20 [	 ]*mvc	16\(1,%r1\),32
.*:	d2 00 10 10 00 20 [	 ]*mvc	16\(1,%r1\),32
.*:	d2 00 00 10 00 20 [	 ]*mvc	16\(1,0\),32
.*:	d2 00 00 10 00 20 [	 ]*mvc	16\(1,0\),32
.*:	d2 00 00 10 00 20 [	 ]*mvc	16\(1,0\),32
.*:	d2 00 00 10 00 20 [	 ]*mvc	16\(1,0\),32
.*:	d2 00 00 10 00 20 [	 ]*mvc	16\(1,0\),32
.*:	d2 00 00 10 00 20 [	 ]*mvc	16\(1,0\),32
.*:	d2 00 00 10 00 20 [	 ]*mvc	16\(1,0\),32
.*:	d2 00 00 10 00 20 [	 ]*mvc	16\(1,0\),32
.*:	d2 00 00 10 00 20 [	 ]*mvc	16\(1,0\),32
.*:	d2 00 00 10 00 20 [	 ]*mvc	16\(1,0\),32
.*:	d2 00 00 10 00 20 [	 ]*mvc	16\(1,0\),32
.*:	d2 00 00 10 00 20 [	 ]*mvc	16\(1,0\),32
.*:	d2 00 00 00 00 00 [	 ]*mvc	0\(1,0\),0
.*:	f3 01 10 10 20 20 [	 ]*unpk	16\(1,%r1\),32\(2,%r2\)
.*:	f3 01 00 10 20 20 [	 ]*unpk	16\(1,0\),32\(2,%r2\)
.*:	f3 01 00 10 20 20 [	 ]*unpk	16\(1,0\),32\(2,%r2\)
.*:	f3 01 00 10 20 20 [	 ]*unpk	16\(1,0\),32\(2,%r2\)
.*:	f3 01 00 10 20 20 [	 ]*unpk	16\(1,0\),32\(2,%r2\)
.*:	f3 01 10 10 00 20 [	 ]*unpk	16\(1,%r1\),32\(2,0\)
.*:	f3 01 10 10 00 20 [	 ]*unpk	16\(1,%r1\),32\(2,0\)
.*:	f3 01 10 10 00 20 [	 ]*unpk	16\(1,%r1\),32\(2,0\)
.*:	f3 01 10 10 00 20 [	 ]*unpk	16\(1,%r1\),32\(2,0\)
.*:	f3 01 00 10 00 20 [	 ]*unpk	16\(1,0\),32\(2,0\)
.*:	f3 01 00 10 00 20 [	 ]*unpk	16\(1,0\),32\(2,0\)
.*:	f3 01 00 10 00 20 [	 ]*unpk	16\(1,0\),32\(2,0\)
.*:	f3 01 00 10 00 20 [	 ]*unpk	16\(1,0\),32\(2,0\)
.*:	f3 01 00 10 00 20 [	 ]*unpk	16\(1,0\),32\(2,0\)
.*:	f3 01 00 10 00 20 [	 ]*unpk	16\(1,0\),32\(2,0\)
.*:	f3 01 00 10 00 20 [	 ]*unpk	16\(1,0\),32\(2,0\)
.*:	f3 01 00 10 00 20 [	 ]*unpk	16\(1,0\),32\(2,0\)
.*:	f3 01 00 10 00 20 [	 ]*unpk	16\(1,0\),32\(2,0\)
.*:	f3 01 00 10 00 20 [	 ]*unpk	16\(1,0\),32\(2,0\)
.*:	f3 01 00 10 00 20 [	 ]*unpk	16\(1,0\),32\(2,0\)
.*:	f3 01 00 10 00 20 [	 ]*unpk	16\(1,0\),32\(2,0\)
.*:	f3 01 00 10 00 20 [	 ]*unpk	16\(1,0\),32\(2,0\)
.*:	f3 01 00 10 00 20 [	 ]*unpk	16\(1,0\),32\(2,0\)
.*:	f3 01 00 10 00 20 [	 ]*unpk	16\(1,0\),32\(2,0\)
.*:	f3 01 00 10 00 20 [	 ]*unpk	16\(1,0\),32\(2,0\)
.*:	f3 01 00 00 00 00 [	 ]*unpk	0\(1,0\),0\(2,0\)
.*:	e7 12 30 10 00 13 [	 ]*vgef	%v1,16\(%v2,%r3\),0
.*:	e7 10 30 10 00 13 [	 ]*vgef	%v1,16\(%v0,%r3\),0
.*:	e7 10 30 10 00 13 [	 ]*vgef	%v1,16\(%v0,%r3\),0
.*:	e7 12 00 10 00 13 [	 ]*vgef	%v1,16\(%v2,0\),0
.*:	e7 12 00 10 00 13 [	 ]*vgef	%v1,16\(%v2,0\),0
.*:	e7 12 00 10 00 13 [	 ]*vgef	%v1,16\(%v2,0\),0
.*:	e7 10 00 10 00 13 [	 ]*vgef	%v1,16\(%v0,0\),0
.*:	e7 10 00 10 00 13 [	 ]*vgef	%v1,16\(%v0,0\),0
.*:	e7 10 00 10 00 13 [	 ]*vgef	%v1,16\(%v0,0\),0
.*:	e7 10 00 10 00 13 [	 ]*vgef	%v1,16\(%v0,0\),0
.*:	e7 10 00 10 00 13 [	 ]*vgef	%v1,16\(%v0,0\),0
.*:	e7 10 00 10 00 13 [	 ]*vgef	%v1,16\(%v0,0\),0
#?.*:	07 07 [	 ]*nopr	%r7
